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March 2001
(R)
AS7C33256PFS16A AS7C33256PFS18A
3.3V 256K x 16/18 pipeline burst synchronous SRAM
Features
* Organization: 262,144 words x 16 or 18 bits * Fast clock speeds to 166 MHz in LVTTL/LVCMOS * Fast clock to data access: 3.5/3.8/4.0/5.0 ns * Fast OE access time: 3.5/3.8/4.0/5.0 ns * Fully synchronous register-to-register operation * "Flow-through" mode * Single-cycle deselect - Dual-cycle deselect also available (AS7C33256PFD16A/ AS7C33256PFD18A)
* Pentium(R)* compatible architecture and timing * Asynchronous output enable control * Economical 100-pin TQFP package * Byte write enables * Multiple chip enables for easy expansion * 3.3V core power supply * 2.5V or 3.3V I/O operation with separate VDDQ * 30 mW typical standby power in power down mode * NTDTM* pipeline architecture available (AS7C33256NTD16A/AS7C33256NTD18A)
Logic block diagram
LBO
CLK ADV ADSC ADSP A[17:0] CLK CS CLR
Pin arrangement
256K x 16/18 Memory array
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
Burst logic
Q
A6 A7 CE0 CE1 NC NC BWb BWa CE2 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A8 A9
18
D CS CLK
18
16 18
Address register
NC NC NC VDDQ VSSQ NC NC DQb DQb VSSQ VDDQ DQb DQb FT VDD NC VSS DQb DQb VDDQ VSSQ DQb DQb DQpb/NC NC VSSQ VDDQ NC NC NC
16/18 16/18
GWE BWb BWE BWa CE0 CE1 CE2 D DQb Q
Byte Write registers Byte Write registers
CLK D CLK D DQa Q
2
OE
Enable Q register Enable Q delay register
CE CLK
Output registers
CLK
Input registers
CLK
ZZ
Power down
D
CLK OE
FT
DATA [17:0] DATA [15:0]
Selection guide
AS7C33256PFS16A AS7C33256PFS16A AS7C33256PFS16A AS7C33256PFS16A -166 -150 -133 -100 Units Minimum cycle time Maximum pipelined clock frequency Maximum pipelined clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC)
*
6 166 3.5 475 130 30
6.7 150 3.8 450 110 30
LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
TQFP 14 x 20mm
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A17 NC NC VDDQ VSSQ NC DQpa/NC DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC
Note: pins 24, 74 are NC for x16.
7.5 133 4 425 100 30
10 100 5 325 90 30
ns MHz ns mA mA mA
Pentium(R) is a registered trademark of Intel Corporation. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners.
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Copyright (c) Alliance Semiconductor. All rights reserved.
AS7C33256PFS16A AS7C33256PFS18A
(R)
Functional description
The AS7C33256PFS16A and AS7C33256PFS18A are high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM) devices organized as 262,144 words x 16 or 18 bits and incorporate a pipeline for highest frequency on any given technology. Timing for this device is compatible with existing Pentium(R) synchronous cache specifications. This architecture is suited for ASIC, DSP (TMS320C6X), and PowerPCTM*-based systems in computing, datacomm, instrumentation, and telecommunications systems. Fast cycle times of 6/6.7/7.5/10 ns with clock access times (tCD) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus frequencies. Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses. Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register. , When ADSP is sampled LOW the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address strobes are HIGH. Burst operation is selectable with the LBO input. With LBO unconnected or driven HIGH, burst operations use a Pentium(R) count sequence. With LBO driven LOW the device uses a linear count sequence suitable for PowerPCTM and many other applications. Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 16/ 18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signal(s). BWn is ignored on the clock edge that samples ADSP LOW but is sampled on all subsequent clock edges. Output buffers are disabled when , . BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW Address is incremented internally to the next burst address if BWn and ADV are sampled LOW . Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow. * ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC. * WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH). * Master chip select CE0 blocks ADSP, but not ADSC. The AS7C33256PFS16A and AS7C33256PFS18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14x20 mm TQFP packaging.
*PowerPCTM is a tradenark International Business Machines Corporation.
Capacitance
Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals Address and control pins I/O pins Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 Unit pF pF
Write enable truth table (per byte)
GWE L H H H
Key: X = Don't Care, L = Low, H = High, T=True, F=False * valid read n = a,b WE, WEn = internal write signal
BWE X L H L
BWn X L X H
WEn T T F* F*
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AS7C33256PFS16A AS7C33256PFS18A
Signal descriptions
Signal CLK A0-A17 DQ[a,b] CE0 I/O I I I/O I Properties CLOCK SYNC SYNC SYNC Description Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock. Address. Sampled when all chip enables are active and ADSC or ADSP are asserted. Data. Driven as output when the chip is enabled and OE is active. Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information. Synchronous chip enables. Active HIGH and active LOW respectively. Sampled on , clock edges when ADSC is active or when CE0 and ADSP are active. Address strobe (processor). Asserted LOW to load a new address or to enter standby mode. Address strobe (controller). Asserted LOW to load a new address or to enter standby mode. Burst advance. Asserted LOW to continue burst read/write. Global write enable. Asserted LOW to write all 16/18 bits. When HIGH, BWE and BW[a,b] control write enable. Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b] inputs. Write enables. Used to control write of individual bytes when GWE = HIGH and BWE = LOW If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the . cycle is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle. Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read mode.
CE1, CE2 ADSP ADSC ADV GWE BWE
I I I I I I
SYNC SYNC SYNC SYNC SYNC SYNC
BW[a,b]
I
SYNC
OE
I
ASYNC
LBO
I
Count mode. When driven HIGH, count sequence follows Intel XOR convention. STATIC default = When driven LOW count sequence follows linear convention. This signal is , HIGH internally pulled HIGH. STATIC ASYNC Flow-through mode.When LOW enables single register flow-through mode. , Connect to VDD if unused or for pipelined operation. Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
FT ZZ
I I
Absolute maximum ratings
Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation DC output current Storage temperature (plastic) Temperature under bias Symbol VDD, VDDQ VIN VIN PD IOUT Tstg Tbias Min -0.5 -0.5 -0.5 - - -65 -65 Max +4.6 VDD + 0.5 VDDQ + 0.5 1.8 50 +150 +135 Unit V V V W mA C C
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.
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AS7C33256PFS16A AS7C33256PFS18A
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Synchronous truth table
CE0 H L L L L L L L L X X X X H H H H L X H X H CE1 X L L X X H H H H X X X X X X X X H X X X X CE2 X X X H H L L L L X X X X X X X X L X X X X ADSP X L H L H L L H H H H H H X X X X H H X H X ADSC L X L X L X X L L H H H H H H H H L H H H H ADV X X X X X X X X X L L H H L L H H X L L H H WEn1 X X X X X X X F F F F F F F F F F T T T T T OE X X X X X L H L H L H L H L H L H X X X X X Address accessed NA NA NA NA NA External External External External Next Next Current Current Next Next Current Current External Next Next Current Current CLK L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H Operation Deselect Deselect Deselect Deselect Deselect Begin read Begin read Begin read Begin read Cont. read Cont. read Suspend read Suspend read Cont. read Cont. read Suspend read Suspend read Begin write Cont. write Cont. write Suspend write Suspend write DQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z2 Hi-Z Hi-Z2 Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z D3 D D D D
Key: X = Don't Care, L = Low, H = High. 1See "Write enable truth table" on page 2 for more information. 2 Q in flow through mode 3 For write operation following a READ, OE must be HIGH before
the input data set up time and held HIGH throughout the input hold
time.
Recommended operating conditions
Parameter Supply voltage 3.3V I/O supply voltage 2.5V I/O supply voltage Address and control pins I/O pins Ambient operating temperature Symbol VDD VSS VDDQ VSSQ VDDQ VSSQ VIH VIL VIH VIL TA Min 3.135 0.0 3.135 0.0 2.35 0.0 2.0 -0.5* 2.0 -0.5* 0 Nominal 3.3 0.0 3.3 0.0 2.5 0.0 - - - - - Max 3.6 0.0 3.6 0.0 2.9 0.0 VDD + 0.3 0.8 VDDQ + 0.3 0.8 70 Unit V V V V V C
Input
voltages
* VIL min = -2.0V for pulse width less than 0.2 x tRC. Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
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AS7C33256PFS16A AS7C33256PFS18A
TQFP thermal resistance
Description Thermal resistance (junction to ambient)* Thermal resistance (junction to top of case)*
* This parameter is sampled.
Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51
Symbol JA JC
Typical 46 2.8
Units C/W C/W
DC electrical characteristics
-166 Parameter Input leakage current* Output leakage current Operating power supply current Symbol |ILI| |ILO| ICC ISB Standby power supply current ISB1 ISB2 Output voltage VOL VOH Test conditions VDD = Max, VIN = GND to VDD OE VIH, VDD = Max, VOUT = GND to VDD CE0 = VIL, CE1 = VIH, CE2 = VIL, f = fMax, IOUT = 0 mA Deselected, f = fMax, ZZ VIL Deselected, f = 0, ZZ 0.2V all VIN 0.2V or VDD - 0.2V Deselected, f = fMax, ZZ VDD - 0.2V All VIN VIL or VIH IOL = 8 mA, VDDQ = 3.465V IOH = -4 mA, VDDQ = 3.135V -150 -133 -100 Min Max Min Max Min Max Min Max Unit - - - - - - - 2.4 2 2 475 130 30 30 0.4 - - - - - - - - 2.4 2 2 450 110 30 30 0.4 - - - - - - - - 2.4 2 2 425 100 30 30 0.4 - - - - - - - - 2.4 2 2 325 90 30 30 0.4 - V mA A A mA
* LBO pin has an internal pull-up and input leakage = 10 a. Note: ICC give with no output loading. ICC increases with faster cycle times and greater output loading.
DC electrical characteristics for 2.5V I/O operation
-166 Parameter Output leakage current Output voltage Symbol |ILO| VOL VOH Test conditions OE VIH, VDD = Max, VOUT = GND to VDD IOL = 2 mA, VDDQ = 2.65V IOH = -2 mA, VDDQ = 2.35V -150 -133 -100 Min Max Min Max Min Max Min Max Unit -1 - 1.7 1 0.7 - -1 - 1.7 1 0.7 - -1 - 1.7 1 0.7 - -1 - 1.7 1 0.7 - A V
Timing characteristics over operating range
-166 Parameter Clock frequency Cycle time (pipelined mode) Cycle time (flow-through mode) Clock access time (pipelined mode) Symbol Min fMax tCYC tCYCF tCD - 6 10 - Max 166 - - 3.5 - 6.6 10 - -150 Min Max 150 - - 3.8 - 7.5 12 - -133 Min Max 133 - - 4.0 - 10 12 - -100 Min Max 100 - - 5.0 Unit MHz ns ns ns Notes*
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AS7C33256PFS16A AS7C33256PFS18A
(R) -166 Parameter Clock access time (flow-through mode) Output enable LOW to data valid Clock HIGH to output Low Z Data output invalid from clock HIGH Output enable LOW to output Low Z Output enable HIGH to output High Z Clock HIGH to output High Z Output enable HIGH to invalid output Clock HIGH pulse width Clock LOW pulse width Address setup to clock HIGH Data setup to clock HIGH Write setup to clock HIGH Chip select setup to clock HIGH Address hold from clock HIGH Data hold from clock HIGH Write hold from clock HIGH Chip select hold from clock HIGH ADV setup to clock HIGH ADSP setup to clock HIGH ADSC setup to clock HIGH ADV hold from clock HIGH ADSP hold fromclock HIGH ADSC hold from clock HIGH
*"Notes" column refers to "notes" on page 10.
-150 Min - - 0 1.5 0 - - 0 2.5 2.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 1.5 1.5 1.5 0.5 0.5 0.5 Max 10 3.8 - - - 3.8 3.8 - - - - - - - - - - - - - - - - -
-133 Min - - 0 1.5 0 - - 0 2.5 2.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 1.5 1.5 1.5 0.5 0.5 0.5 Max 10 4.0 - - - 4.0 4.0 - - - - - - - - - - - - - - - - -
-100 Min - - 0 1.5 0 - - 0 3.5 3.5 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 2.0 2.0 2.0 0.5 0.5 0.5 Max 12 5.0 - - - 4.5 5.0 - - - - - - - - - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 5 6 6 6,7 6,8 6 6 6,7 6,8 6 6 6 6 6 6 2,3,4 2 2,3,4 2,3,4 2,3,4 Notes*
Symbol Min tCDF tOE tLZC tOH tLZOE tHZOE tHZC tOHOE tCH tCL tAS tDS tWS tCSS tAH tDH tWH tCSH tADVS tADSPS tADSCS tADVH tADSPH tADSCH - - 0 1.5 0 - - 0 2.4 2.4 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 1.5 1.5 1.5 0.5 0.5 0.5
Max 9 3.5 - - - 3.5 3.5 - - - - - - - - - - - - - - - - -
Key to switching waveforms
Rising input Falling input Undefined/don't care
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AS7C33256PFS16A AS7C33256PFS18A
Timing waveform of read cycle
tCH CLK tADSPS tADSPH ADSP tADSCS tADSCH ADSC tAS tAH Address A1 tWS tWH GWE, BWE tCSS tCSH CE0, CE2 A2 A3 LOAD NEW ADDRESS tCYC tCL
CE1 tADVS tADVH ADV OE tHZOE tOH DOUT (pipelined mode) t OE tLZOE DOUT (flow-through mode) Q(A1) Q(A2)
Q(A2Y01)
tCD ADV INSERTS WAIT STATES tHZC Q(A2Y10)
Q(A2Y11) Q(A3) Q(A3Y01) Q(A3Y10)
Q(A1)
Q(A2Y01)
Q(A2Y10)
Q(A2Y11)
Q(A3)
Q(A3Y01)
Q(A3Y10)
Q(A3Y11) tHZC
Note: Y = XOR when MODE = HIGH/No Connect; Y = ADD when MODE = LOW. BW[a:b] is don't care.
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AS7C33256PFS16A AS7C33256PFS18A
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Timing waveform of write cycle
tCYC tCH CLK tADSPS tADSPH ADSP tCL
tADSCS tADSCH ADSC
tAS tAH Address A1 A2
ADSC LOADS NEW ADDRESS A3
tWS BWE BWa,b tWH
tCSS tCSH CE0, CE2
CE1 ADV SUSPENDS BURST ADV tADVS tADVH
OE tDS tDH Data In
D(A1) D(A2) D(A2Y01) D(A2Y01) D(A2Y10) D(A2Y11) D(A3) D(A3Y01) D(A3Y10)
Note: Y = XOR when MODE = HIGH/No Connect; Y = ADD when MODE = LOW.
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AS7C33256PFS16A AS7C33256PFS18A
Timing waveform of read/write cycle
tCYC tCH CLK tADSPS tADSPH ADSP tAS tAH Address A1 A2 tWS tWH GWE A3 tCL
CE0, CE2
CE1 tADVS tADVH ADV
OE tDS tDH DIN tLZC tCD DOUT (pipeline mode) tCDF DOUT (flow-through mode) Q(A1)
Q(A3Y01) Q(A3Y10) Q(A3Y11)
D(A2) tHZOE tLZOE tOE Q(A3)
Q(A3Y01) Q(A3Y10) Q(A3Y11)
tOH
Q(A1)
Note: Y = XOR when MODE = HIGH/No Connect; Y = ADD when MODE = LOW.
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AS7C33256PFS16A AS7C33256PFS18A
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AC test conditions
* Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C. * Input pulse level: GND to 3V. See Figure A. * Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A. * Input and output timing reference levels: 1.5V. +3.0V Z0 = 50 90% 90% 10% DOUT 50 VL = 1.5V for 3.3V I/O; 30 pF* = V DDQ/2 for 2.5V I/O DOUT 351 +3.3V for 3.3V I/O; +2.5V for 2.5V I/O 317 5 pF* GND *including scope and jig capacitance Thevenin equivalent:
10% GND
Figure A: Input waveform
Notes
Figure B: Output load (A)
Figure C: Output load(B)
1) For test conditions, see AC Test Conditions, Figures A, B, C. 2) This parameter measured with output load condition in Figure C. 3) This parameter is sampled, but not 100% tested. 4) tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage. 5) tCH measured as HIGH above VIH and tCL measured as LOW below VIL. 6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled. 7) Write refers to GWE, BWE, BW[a:d]. 8) Chip select refers to CE0, CE1,
CE2.
Package Dimensions
100-pin quad flat pack (TQFP)
TQFP Min Max 0.05 0.15 1.35 1.45 0.22 0.38 0.09 0.20 13.90 14.10 19.90 20.10 0.65 nominal 15.90 16.10 21.90 22.10 0.45 0.75 1.00 nominal 0 7
Hd D b
A1 A2 b c D E e Hd He L L1
e
He E
Dimensions in millimeters c L1 L A1 A2
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AS7C33256PFS16A AS7C33256PFS18A
Ordering information
-166 MHz AS7C33256PFS16A-166TQC AS7C33256PFS16A-166TQI AS7C33256PFS18A-166TQC AS7C33256PFS18A-166TQI -150 MHz AS7C33256PFS16A-150TQC AS7C33256PFS16A-150TQI AS7C33256PFS18A-150TQC AS7C33256PFS18A-150TQI -133 MHz AS7C33256PFS16A-133TQI AS7C33256PFS18A-133TQI -100 MHz AS7C33256PFS16A-100TQI AS7C33256PFS18A-100TQI AS7C33256PFS16A-133TQC AS7C33256PFS16A-100TQC AS7C33256PFS18A-133TQC AS7C33256PFS18A-100TQC
Part numbering guide
AS7C 1 33 2 256 3 PF 4 S 5 16/18 6 A 7 -XXX 8 TQ 9 C/I 10
1.Alliance Semiconductor SRAM prefix 2.Operating voltage: 33=3.3V 3.Organization: 256=256K 4.Pipeline-Flowthrough (each device works in both modes) 5.Deselect: S=Single cycle deselect 6.Organization: 16=x16; 18=x18 7.Production version: A=first production version 8.Clock speed (MHz) 9.Package type: TQ=TQFP 10.Operating temperature: C=Commercial (0 C to 70 C); I=Industrial (-40 C to 85 C)
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(c) Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

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